I. Field of the Invention
The present invention relates generally to signal processing systems, and specifically to devices for generating signal delays of controlled, variable duration.
II. Related Art
The sophistication of communication systems is rapidly increasing. For example, a communication system may include an array of satellites which serve as relay stations. In developing an apparatus which uses the array of satellites, it is desirable to test the apparatus during development without placing the satellites in orbit. In such a case it is desirable to have a simulator which simulates the operation of the array of satellites. A major component of such a simulator is a delay generator which accurately delays signals for calculated periods. Due to simulated motion of the satellites, the delay varies dynamically over time.
A standard delay generator receives as input samples of an input signal and provides the samples as an output after their respective delays. Since the delay may be different for each sample, the output samples are not synchronized with each other or with the input. The lack of synchronization imposes constraints on apparatus receiving the output samples for further processing, for example, on a digital-to-analog converter or other circuits operating on a fixed, synchronous clock.
U.S. Pat. No. 4,907,247, to Miyake et al., which is incorporated herein by reference, describes a satellite simulation system in which multiple digital satellite communication terminals are interconnectable over multiple channels. The equipment includes a single satellite delay simulator intervening between transmit communication terminals and receive communication terminals. The delay simulator is implemented by a satellite delay circuit accommodating multiple channels and clock matching circuits. The communication terminals are individually connectable to the delay circuit via the clock matching circuits.
It is an object of some aspects of the present invention to provide a delay generator which provides a synchronized output.
It is another object of some aspects of the present invention to provide methods and apparatus for delaying signals for a predetermined period and providing the delayed signals synchronously.
It is still another object of some aspects of the present invention to provide a delay generator whose output is synchronized with its input.
In preferred embodiments of the present invention, a delay generator receives samples of an input signal which have been sampled at a constant clock rate and calculates for each sample the required time it is to be delayed. Rather than delaying each sample by the required delay time, however, the samples are actually delayed so as to remain in synchronization with the clock rate. The values of the delayed samples are corrected to compensate for the difference between the actual delay time and the required delay time, which difference is evaluated to a resolution substantially greater than the clock rate, typically by orders of magnitude. Adjusting the delayed samples to be in synchronization with the input samples, and using the difference to evaluate the delayed sample, significantly simplifies construction and operation of other processing circuitry associated with the delay generator.
In some preferred embodiments of the present invention, the required time by which each sample is to be delayed is calculated by integration. At the beginning of a simulation session an actual delay, and a first differential of the actual delay, are calculated and are loaded into respective registers of an integrator. Preferably, new precalculated values of the differential are loaded into its register at predetermined times during the simulation. During the simulation, the integrator iteratively calculates new values of the actual delay, and updates the appropriate register.
In some preferred embodiments of the present invention, the delay generator comprises a first-in first-out (FIFO) unit which provides the actual delay, and an interpolation filter which corrects the values of the samples. The FIFO unit preferably provides the delay to a sample by writing the sample into a memory and reading the sample from the memory after an integral number of cycles of the clock driving the FIFO unit. The period of the clock driving the FIFO unit is referred to herein as a delay step. Preferably, the compensated value for a particular input sample is calculated by interpolation between a number of input samples, so as to correct for the difference between the precise, required delay time and the actual delay time defined in clock cycle steps. Most preferably, the value of the corrected sample is interpolated based on four neighboring samples. Further preferably, the filter handles I and Q samples separately due to their phase difference.
In some preferred embodiments of the present invention, the required delay is a continuous function which changes slowly relative to the delay step. Preferably, a sequence of samples are written into the memory at consecutive addresses and are read from consecutive addresses in the memory. Further preferably, the samples are read from the memory at a constant rate while the samples are written into the memory at a rate which depends on changes in the number of delay steps required from the FIFO unit. Preferably, when a simulation period is started, beginning read and write addresses are assigned to the memory and they are thereafter updated consecutively with each read and write operation, respectively. When the required delay remains substantially constant, read and write operations are performed at the same rate. However, when the required delay increases by an amount greater than the size of the delay step, two write operations are performed in the time a single read is performed. Conversely, when the required delay decreases by an amount greater than the size of the delay step, a cycle without a write operation is performed.
In a preferred embodiment of the present invention, the delay generator is used in order to simulate the transmission of the samples from a base station, via a satellite, to a receiver. Preferably, the delay generator forms part of a multi-channel simulation system as described in a U.S. Patent application Ser. No. 09/531,981 entitled xe2x80x9cSatellite Motion Simulator,xe2x80x9d filed on even date, which is assigned to the assignee of the present patent application and whose disclosure is incorporated herein by reference.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a method for generating a variable delay of a signal, including: providing a clock indicating a sequence of sample times at regular intervals; receiving a sequence of input samples representing input values of the signal at respective sample times indicated by the clock; determining the delay with a temporal resolution substantially finer than the clock interval to be applied to the signal at each of the respective sample times; and for each of the sample times, responsive to the respectively-determined delay, processing one or more of the input samples so as to generate a corresponding output sample representing a delayed output value of the signal at the sample time.
Preferably, the method includes outputting the samples at the regular intervals indicated by the clock.
Preferably, determining the delay includes calculating a delay responsive to a parameter that varies over time, most preferably by calculating a delay that varies from one sample to the next.
Preferably, determining the delay includes determining a delay induced by transmission of the signal through a communications link.
Preferably, determining the delay includes utilizing a process of integration to determine the delay, most preferably utilizing a precalculated differential of the delay based on a model of motion of an object with which the delay is associated.
Preferably, processing the input samples includes dividing the delay into a coarse and a fine component.
Preferably, the coarse component includes the largest number of clock intervals by which the determined delay can be divided, and the fine component includes the remainder of the division. Preferably, processing the input samples includes interpolating between the samples to compute the output sample responsive to the fine component. Most preferably, interpolating between the samples includes assigning respective predetermined coefficients to the one or more input samples, wherein the predetermined coefficients are selected responsive to a magnitude of the fine delay component relative to the clock interval.
Preferably, processing the input samples includes writing the samples to a write address in a memory and reading the samples from a read address therein, wherein the read and write addresses are separated by a difference responsive to a magnitude of the coarse component of the delay.
Preferably, writing the samples includes writing a sample twice in the time of a single read operation when the delay increases. Preferably, writing the samples includes not writing a sample in the time of a read operation when the delay decreases.
There is further provided, in accordance with a preferred embodiment of the present invention, a variable delay generator, which receives as input a sequence of samples of a signal at sample times indicated by a sample clock having a predetermined clock period, and which includes: a delay controller, which determines a variable delay having a temporal resolution substantially finer than the clock interval to be applied to the signal at each of the respective sample times; and a delay line which receives the input sequence of samples and outputs a synchronous stream of output samples at the sample times, each output sample representing a respective value of the signal following the delay determined by the delay controller.
Preferably, the delay controller divides the delay into a coarse and a fine component.
Preferably, the delay line includes an interpolation filter which interpolates among the input samples to generate a value of the output sample dependent on the fine component. Most preferably, the interpolation filter selects interpolation coefficients from among a plurality of predetermined coefficients, which are respectively assigned to the sequence of input samples.
Preferably, the delay unit includes a coarse delay unit which delays the output samples by the coarse component. Preferably, the coarse delay unit includes a first-in first-out memory device, wherein the samples are written to a write address therein and wherein the samples are read from a read address therein, wherein the read and write addresses are separated by a difference responsive to the delay.
Preferably, the delay controller iteratively calculates the delay. Most preferably, the delay controller includes an integrator to determine the variable delay for each of the samples based on a precalculated differential of the delay.